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K3N4C1000D-D(G)C
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM
FEATURES
* Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode) * Fast access time : 100ns(Max.) * Supply voltage : single +5V * Current consumption Operating : 50mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. K3N4C1000D-DC : 42-DIP-600 -. K3N4C1000D-GC : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The K3N4C1000D-D(G)C is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x16 bit(word mode) depending on BHE voltage level. (See mode selection table) This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3N4C1000D-DC is packaged in a 42-DIP and the K3N4C1000D-GC in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A18 . . . . . . . . A0 A-1
X BUFFERS AND DECODER
MEMORY CELL MATRIX (524,288x16/ 1,048,576x8)
A18 A17 A7 A6 A5
1 2 3 4 5 6 7 8 9
42 N.C 41 A8 40 A9 39 A10 38 A11 37 A12 36 A13 35 A14 34 A15 33 A16 32 BHE 31 VSS 30 Q15/A-1 29 Q7 28 Q14 27 Q6 26 Q13 25 Q5 24 Q12 23 Q4 22 VCC
N.C 1 A18 A17 A7 A6 A5 A4 A3 A2 2 3 4 5 6 7 8 9
44 N.C 43 N.C 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BHE 32 VSS 31 Q15/A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS
A4 A3 A2 A1
A0 10 CE 11 VSS 12 OE 13 Q0 14
A1 10 A0 11 CE 12 VSS 13 OE 14 Q0 15 Q8 16 Q1 17 Q9 18 Q2 19 Q10 20 Q3 21 Q11 22
...
CE OE BHE CONTROL LOGIC Q0/Q8 Q7/Q15
DIP
SOP
Q8 15 Q1 16 Q9 17 Q2 18 Q10 19 Q3 20
Pin Name A0 - A18 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C
Pin Function Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power ( +5V) Ground No Connection
Q11 21
K3N4C1000D-DC K3N4C1000D-GC
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K3N4C1000D-D(G)C
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating
CMOS MASK ROM
Unit V C C
-0.3 to +7.0 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions Cycle=5MHz, all outputs open CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.2 -0.3 2.4 Max 50 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA A A A V V V V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N4C1000D-D(G)C
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0C to +70C, VCC=5.0V10%, unless otherwise noted.)
0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 K3N4C1000DD(G)C10 Min 100 100 100 50 20 0 Max K3N4C1000DD(G)C12 Min 120 120 120 60 20 0 Max K3N4C1000DD(G)C15 Min 150 150 150 70 30 Max ns ns ns ns ns ns Unit
TIMING DIAGRAM
READ
ADD A0~A18 A-1(*1) tACE CE
ADD1 tRC
ADD2 tDF(*3)
tOE OE
tAA
tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA
NOTES : *1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

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